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K4S510832M

Part Number	K4S510832M
Manufacturer	Samsung semiconductor
Description	16M x 8bit x 4 Banks Synchronous DRAM LVTTL
Published	Jul 14, 2007
Detailed Description	K4S510832M Preliminary CMOS SDRAM 512Mbit SDRAM 16M x 8bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revi...
Datasheet	K4S510832M PDF File

Overview

K4S510832M Preliminary CMOS SDRAM 512Mbit SDRAM 16M x 8bit x 4 Banks Synchronous DRAM LVTTL www.
DataSheet4U.
com Revision 0.
2 Dec.
2001 Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
2 Dec.
2001 K4S510832M Revision History Revision 0.
0 (Mar.
2001) Revision 0.
1 (Aug.
2001) Defined target DC characteristics.
Preliminary CMOS SDRAM Revision 0.
2 (Dec.
2001) • • Changed "Target" to "Preliminary".
Redefined DC characteristics.
Rev.
0.
2 Dec.
2001 K4S510832M 16M x 8Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (8K cycle) Part No.
K4S510832M-TC/TL75 K4S510832M-TC/TL1H K4S510832M-TC/TL1L Preliminary CMOS SDRAM GENERAL DESCRIPTION The K4S510832M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION Max Freq.
133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL Interface Package 54pin TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 16M x 8 16M x 8 16M x 8 16M x 8 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col.
Buffer Latency & Burst Length LRAS LCBR L...

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