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XRT94L31

Exar Corporation
Part Number XRT94L31
Manufacturer Exar Corporation
Description 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
Published Aug 23, 2007
Detailed Description www.DataSheet4U.com MARCH 2007 XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC REV. 1.0.1 GENERAL DESCRIPTION...
Datasheet PDF File XRT94L31 PDF File

XRT94L31
XRT94L31

Overview
www.
DataSheet4U.
com MARCH 2007 XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC REV.
1.
0.
1 GENERAL DESCRIPTION The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream.
The XRT94L31 interfaces directly to the optical transceiver.
The XRT94L31 processes the section, line and path overhead in the SONET/SDH data stream.
The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes.
Path overhead bytes can be accessed through the microprocessor interface or via serial interface.
The XRT94L31 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements.
These De-Synchronizer circuits do not need any external clock reference for its operation.
The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software.
Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L31 memory map or from external interface.
A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated.
The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing.
The XRT94L31 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary.
The XRT94L31 provides 3 mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers.
A PRBS test pattern generation and detection is implemented to measure the bit-error performance.
A general-purpose microprocessor interface is included for control, configuration and monitoring.
APPLICATIONS • Network switches • Add/Drop Multiplexer • W-DCS Digital Cross Connect Systems FEATURES • Provides DS3/ E3 mapping/de-ma...


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