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25AA1024

Microchip Technology
Part Number 25AA1024
Manufacturer Microchip Technology
Description 1 Mbit SPI Bus Serial EEPROM
Published Sep 5, 2007
Detailed Description 25AA1024 1 Mbit SPI Bus Serial EEPROM Device Selection Table Part Number 25AA1024 VCC Range 1.8-5.5V Page Size 256 ...
Datasheet PDF File 25AA1024 PDF File

25AA1024
25AA1024


Overview
25AA1024 1 Mbit SPI Bus Serial EEPROM Device Selection Table Part Number 25AA1024 VCC Range 1.
8-5.
5V Page Size 256 Byte Temp.
Ranges I Packages P, SM, MF Features • 20 MHz Maximum Clock Speed • Byte and Page-level Write Operations: - 256 byte page - 6 ms maximum write cycle time - No page or sector erase required • Low-Power CMOS Technology: - Maximum Write current: 7 mA at 5.
5V - Maximum Read current: 10 mA at 5.
5V, 20 MHz - Standby current: 1 µA at 2.
5V, 85°C (Deep Power-down) • Electronic Signature for Device ID • Self-Timed Erase and Write Cycles: - Page Erase (6 ms maximum) - Sector Erase (10 ms maximum) - Chip Erase (10 ms maximum) • Sector Write Protection (32K byte/sector): - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • High Reliability: - Endurance: 1M erase/write cycles - Data Retention: >200 years - ESD Protection: 4000V • Temperature Ranges Supported: - Industrial (I):-40°C to +85°C • RoHS Compliant Pin Function Table Name Function CS SO WP VSS SI SCK HOLD VCC Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage Description The Microchip Technology Inc.
25AA1024 is a 1024 Kbit serial EEPROM memory with byte-level and page-level serial EEPROM functions.
It also features Page, Sector and Chip erase functions typically associated with Flash-based products.
These functions are not required for byte or page write operations.
The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled by a Chip Select (CS) input.
Communication to the device can be paused via the hold pin (HOLD).
While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to servi...



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