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89HPES16NT2

IDT
Part Number 89HPES16NT2
Manufacturer IDT
Description 16-Lane 2-Port Non-Transparent PCI Express Switch
Published Oct 1, 2007
Detailed Description www.DataSheet4U.com 16-Lane 2-Port Non-Transparent PCI Express® Switch 89HPES16NT2 Product Brief Device Overview The...
Datasheet PDF File 89HPES16NT2 PDF File

89HPES16NT2
89HPES16NT2

Overview
www.
DataSheet4U.
com 16-Lane 2-Port Non-Transparent PCI Express® Switch 89HPES16NT2 Product Brief Device Overview The 89HPES16NT2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect standard.
The PES16NT2 is a 16-lane, 2-port peripheral chip that provides high-performance switching and non-transparent bridging (NTB) functions between a PCIe® upstream port and an NTB downstream port.
The PES16NT2 is a part of the IDT PCIe System Interconnect Products and is intended to be used with IDT PCIe System Interconnect Switches.
Together, the chipset targets multi-host and intelligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required.
Features High Performance PCI Express Switch – Sixteen PCI Express lanes (2.
5Gbps), two switch ports – Delivers 64 Gbps (8 GBps) of aggregate switching capacity – Low latency cut-through switch architecture – Support for Max Payload size up to 2048 bytes – Supports one virtual channel and eight traffic classes – PCI Express Base specification Revision 1.
0a compliant ◆ Flexible Architecture with Numerous Configuration Options – Supports automatic per port link width negotiation (x8, x4, x2, or x1) – Static lane reversal on all ports – Automatic polarity inversion on all lanes ◆ – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Non-Transparent Port – Crosslink support on NTB port – Four mapping windows supported • Each may be configured as a 32-bit memory or I/O window • May be paired to form a 64-bit memory window – Interprocessor communication • Thirty-two inbound and outbound doorbells • Four inbound and outbound message registers • Two shared scratchpad registers – Allows up to sixteen masters to communicate through the nontransparent port – No limit on the number of supported outstanding transact...


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