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ICSSSTUAF32866C

IDT
Part Number ICSSSTUAF32866C
Manufacturer IDT
Description 25-BIT CONFIGURABLE REGISTERED BUFFER
Published Oct 2, 2007
Detailed Description www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF3...
Datasheet PDF File ICSSSTUAF32866C PDF File

ICSSSTUAF32866C
ICSSSTUAF32866C

Overview
www.
DataSheet4U.
com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high.
If either DCS and CSR input is low, the Qn outputs will function normally.
The RESET input has priority over the DCS and CSR control and will force the outputs low.
If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data i...


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