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IDT74SSTUBF32868A

IDT
Part Number IDT74SSTUBF32868A
Manufacturer IDT
Description 28-BIT CONFIGURABLE REGISTERED BUFFER
Published Oct 3, 2007
Detailed Description www.DataSheet4U.com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBF32868A occurred on the open-d...
Datasheet PDF File IDT74SSTUBF32868A PDF File

IDT74SSTUBF32868A
IDT74SSTUBF32868A

Overview
www.
DataSheet4U.
com DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBF32868A occurred on the open-drain QERR pin (active low).
The convention is even parity, i.
e.
, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low.
If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low.
If a parity error occurs on the clock cycle before the device enters the low-power (LPM) and the QERR output is driven low, then it stays lateched low for the LPM duration plus two clock cycles or until RESET is driven low.
The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DC...


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