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HYS72T128920

Qimonda
Part Number HYS72T128920
Manufacturer Qimonda
Description (HYSxxTxxxxx0) 240-Pin Unbuffered DDR2 SDRAM Modules
Published Oct 10, 2007
Detailed Description www.DataSheet4U.com October 2006 HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 H...
Datasheet PDF File HYS72T128920 PDF File

HYS72T128920
HYS72T128920

Overview
www.
DataSheet4U.
com October 2006 HYS64T32[0/9]00EU-[25F/2.
5/3/3S/3.
7]-B2 HYS[64/72]T64[0/9]00EU-[25F/2.
5/3/3S/3.
7]-B2 HYS[64/72]T128[0/9]20EU-[25F/2.
5/3/3S/3.
7]-B2 2 4 0 - P i n u n b u f f e r e d D D R 2 S D R A M Mo d u l e s DDR2 SDRAM UDIMM SDRAM RoHs Compliant Internet Data Sheet Rev.
1.
0 www.
DataSheet4U.
com Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.
5/3/3S/3.
7]-B2 Unbuffered DDR2 SDRAM Module HYS64T32[0/9]00EU-[25F/2.
5/3/3S/3.
7]-B2, HYS[64/72]T64[0/9]00EU-[25F/2.
5/3/3S/3.
7]-B2, HYS[64/72]T128[0/9]20EU[25F/2.
5/3/3S/3.
7]-B2 Revision History: 2006-10, Rev.
1.
0 Page All All 4,5 16 – 20 34, 35 38 – 42 45 – 92 Subjects (major changes since last revision) Qimonda update Adapted internet edition Ordering information table.
Added 6LayerWhiteBox Products Block Diagrams: Clock Signal Load Tables and Notes updated ODT table update Added IDD values SPD codes updated Previous Revision: 2006-07, Rev.
0.
5 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-08-07 10202006-L0SM-FEYT 2 w w w .
D a t a S h e e t 4 U .
c o m Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.
5/3/3S/3.
7]-B2 Unbuffered DDR2 SDRAM Module 1 Overview This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main characteristics.
1.
1 Features • • • • • • • • • • Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.
8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM UDIMM Dimensions (nominal): 30 mm high and 133.
35 mm wide Based on stand...


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