DatasheetsPDF.com

ICS8MJ0

Integrated Circuit Systems
Part Number ICS8MJ0
Manufacturer Integrated Circuit Systems
Description (ICS8Mx0) Crystal Oscillator
Published Dec 1, 2007
Detailed Description www.DataSheet4U.com Integrated Circuit Systems, Inc. PRELIMINARY ICS8Mx0 OUT VDD Crystal Oscillator: LVCMOS/LVTTL CL...
Datasheet PDF File ICS8MJ0 PDF File

ICS8MJ0
ICS8MJ0

Overview
www.
DataSheet4U.
com Integrated Circuit Systems, Inc.
PRELIMINARY ICS8Mx0 OUT VDD Crystal Oscillator: LVCMOS/LVTTL CLOCK OUTPUT ICS8Mx0 LOW JITTER, HIGH FREQUENCY XTAL OSCILLATOR • (including initial accuracy, operating temperature variation, supply voltage variation, load variation, reflow drift, and aging for 10 years) Low phase jitter < 1 ps rms maximum (12kHz to 20MHz) 4-pin CERHERMETIC 5 x 7 x 1.
5mm SMT ELECTRICAL SPECIFICATIONS Unless stated otherwise, VDD = 3.
3 Volts + 0.
3V or 2.
5 Volts + 5%, TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), CL < 25pF Parameter Min Typ Max Unit Conditions DC CHARACTERISTICS Power Supply Voltage VDD 3.
0 3.
3 3.
6 V 3.
3V operation Power Supply 2.
375 2.
5 2.
625 V 2.
5V operation in 8MJ0 and 8MK0 only (VDD pin) Power Supply Current IDD 75 mA OE = VDD Current with Output Disable Input Capacitance Output Enable Input High Voltage (OE pin) LVCMOS/LVTTL Input Low Voltage Input High Current Input Low Current Internal Pull-up Resistor Output High Voltage1 Clock Output Level Output Low Voltage1 (OUT pin) LVCMOS/LVTTL Output Load Condition (fan out) Output Impedance AC CHARACTERISTICS Output Frequency Range Output Frequency Stability error (OUT pin) Output Duty Cycle Output Rise Time Output Fall Time Oscillator Start-up Time IOED CIN VIH VIL IIH IIL RPULLUP VOH VOL CL ROUT 5 75 ∆f/fO odc tR tF tOSC 50 1.
5 1.
5 10 7 VDD - 0.
4 0.
4 25 12 250 ±100 ±50 -150 51 0.
7 x VDD 5 4 <0.
6 mA pF V 0.
3 x VDD V µA µA kΩ V V pF Ω MHz ppm p-p ppm p-p % ns ns ms in 8MH0 and 8MK0 in 8MG0 and 8MJ0 All conditions Includes frequency set, VDD, TA & load variation, reflow drift, 10 yr.
aging VTH = VDD / 2 , CL < Max.
pF 20% to 80% of VDD , CL < Max.
pF Time at Min.
VDD (3.
0V or 2.
375V) to be 0s (design target) Deterministic Random Root Mean Square Peak to Peak Accumulated Jitter n = 2 to 50,000 cycles σ of Random jitter σ of Total jitter distribution fO < 250MHz VDD = 3.
3V + 0.
3V or 2.
5V + 5% VDD = VIN = 3.
6V or 2.
625V VDD = 3.
6V or 2.
625V,...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)