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GS864236B-xxxV

GSI Technology
Part Number GS864236B-xxxV
Manufacturer GSI Technology
Description (GS8642xxB/C-xxxV) 4M x 18 / 2M x 36/ 1M x 72 72Mb S/DCD Sync Burst SRAMs
Published Jan 3, 2008
Detailed Description www.DataSheet4U.com Preliminary GS864218/36/72(B/C)-xxxV 119- & 209-Pin BGA Commercial Temp Industrial Temp Features ...
Datasheet PDF File GS864236B-xxxV PDF File

GS864236B-xxxV
GS864236B-xxxV

Overview
www.
DataSheet4U.
com Preliminary GS864218/36/72(B/C)-xxxV 119- & 209-Pin BGA Commercial Temp Industrial Temp Features 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs 250 MHz–167 MHz 1.
8 V or 2.
5 V VDD 1.
8 V or 2.
5 V I/O • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.
1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 1.
8 V or 2.
5 V core power supply • 1.
8 V or 2.
5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119- and 209-bump BGA package • RoHS-compliant 119- and 209-bump BGA packages available Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode .
Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads The GS864218/36/72(B/C)-xxxV is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
DCD SRAMs pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
The user may configure this SRAM for either mode of operation using the SCD mode input.
Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined...


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