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GS84118B

GSI Technology
Part Number GS84118B
Manufacturer GSI Technology
Description 256K x 18 Sync Cache Tag
Published Feb 28, 2008
Detailed Description www.DataSheet4U.com GS84118T/B-166/150/133/100 TQFP, BGA Commercial Temp Industrial Temp Features • 3.3 V +10%/–5% core...
Datasheet PDF File GS84118B PDF File

GS84118B
GS84118B

Overview
www.
DataSheet4U.
com GS84118T/B-166/150/133/100 TQFP, BGA Commercial Temp Industrial Temp Features • 3.
3 V +10%/–5% core power supply, 2.
5 V or 3.
3 V I/O supply • Intergrated data comparator for Tag RAM application • FT mode pin for flow through or pipeline operation • LBO pin for Linear or Interleave (PentiumTM and X86) Burst mode • Synchronous address, data I/O, and control inputs • Synchronous Data Enable (DE) • Asynchronous Output Enable (OE) • Asynchronous Match Output Enable (MOE) • Byte Write (BWE) and Global Write (GW) operation • Three chip enable signals for easy depth expansion • Internal self-timed write cycle • JTAG Test mode conforms to IEEE standard 1149.
1 • JEDEC-standard 100-lead TQFP package and 119-BGA: T:TQFP or B: BGA -166 Pipeline 3-1-1-1 Flow Through 2-1-1-1 tcycle tKQ IDD tKQ tcycle IDD 6.
0 ns 3.
5 ns 310 mA 8.
5 ns 10 ns 190 mA -150 6.
6 ns 3.
8 ns 275 mA 10 ns 10 ns 190 mA -133 7.
5 ns 4.
0 ns 250 mA 11 ns 15 ns 140 mA -100 10 ns 4.
5 ns 190 mA 12 ns 15 ns 140 mA 256K x 18 Sync Cache Tag 166 MHz–100 MHz 8.
5 ns–12 ns 3.
3 V VDD 3.
3 V and 2.
5 V I/O Output registers and the Match output register are provided and controlled by the FT mode pin (Pin 14).
Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation.
Flow Through mode reduces latency.
Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2.
In addition, Global Write (GW) is available for writing all bytes at one time.
Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register.
The comparator compares the read data with the registered input data and a match signal is generated.
The match output can be either in Pipeline or Flow Through modes controlled by the FT signal.
Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK).
Memory data is retained during ...


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