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DM9131

Davicom Semiconductor Incorporated
Part Number DM9131
Manufacturer Davicom Semiconductor Incorporated
Description 10/100Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Published Mar 28, 2008
Detailed Description www.DataSheet4U.com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver General Description The DM9...
Datasheet PDF File DM9131 PDF File

DM9131
DM9131

Overview
www.
DataSheet4U.
com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver General Description The DM9131 is a physical-layer, single-chip, lowpower transceiver for 100BASE-TX and 10BASE-T operations.
On the media side, it provides a direct interface either to Unshielded Twisted Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet, and it also provides PECL interface to connect the external fiber optical transceiver.
Through the Media Independent Interface (MII), the DM9131 connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors.
The DM9131 uses a low-power and high-performance CMOS process.
It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.
3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The DM9131 provides a strong support for the autonegotiation function utilizing automatic media speed and protocol selection.
Furthermore, due to the builtin wave-shaping filter, the DM9131 needs no external filter to transport signals to the media in 100M or 10M Ethernet operation.
Block Diagram 100Base-FX PECL Interface 100Base-TX Transceiver 100BaseTX PCS MII Interface 10Base-T TX/RX Module LED Driver Auto-Negotiation Clock Circuit Block Biasing/ Power Block MII Register MII Management Control Final Version: DM9131-DS-F01 April 7, 2000 1 www.
DataSheet4U.
com DM9131 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Table of Contents General Description .
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1 DAVICOM Specified Interrupt Register - 21 20 Block Diagram.
1 Features 3 Pin Configuration: DM9101E LQFP ...


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