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ASM5I9351

Part Number	ASM5I9351
Manufacturer	Alliance Semiconductor
Description	9-Output Zero Delay Buffer
Published	May 9, 2008
Detailed Description	July 2005 rev 0.2 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Features Output frequency range: 25 MHz to 200...
Datasheet	ASM5I9351 PDF File

Overview

July 2005 rev 0.
2 2.
5V or 3.
3V, 200 MHz, 9-Output Zero Delay Buffer Features Output frequency range: 25 MHz to 200 MHz Input frequency range: 25 MHz to 200 MHz 2.
5V or 3.
3V operation ASM5I9351 The ASM5I9351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2, and 5 outputs.
Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see Table.
2.
These dividers allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4.
Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines.
For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz.
This allows a wide range of output frequencies from 25 MHz to 200 MHz.
For normal operation, the external feedback input, FB_IN, is connected to one of the outputs.
The internal VCO is running at multiples of the input reference clock set by the feedback divider, see the Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference Split 2.
5V/3.
3V outputs www.
DataSheet4U.
com ± 2.
5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: LVPECL or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode ‘SpreadTrak’ Output enable/disable Pin-compatible with MPC9351 and CY29351.
Industrial temperature range: –40°C to +85°C 32-pin 1.
0mm TQFP & LQFP Package.
Functional Description The ASM5I9351 is a low voltage high performance clock directly feeds the output dividers.
This mode is fully static and the minimum input clock frequency specification does not apply.
200MHz PLL-based zero delay buffer designed for high speed clock distribution applications.
Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.
855.
4900 • Fax: 408.
855...

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