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MPC9653

Part Number	MPC9653
Manufacturer	Motorola
Description	3.3V 1:8 LVCMOS PLL CLOCK GENERATOR
Published	Jul 5, 2008
Detailed Description	MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9653/D Rev 3, 02/2003 3.3V 1:8 ...
Datasheet	MPC9653 PDF File

Overview

MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9653/D Rev 3, 02/2003 3.
3V 1:8 LVCMOS PLL Clock Generator MPC9653 The MPC9653 is a 3.
3V compatible, 1:8 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications.
With output frequencies up to 125 MHz and output skews less than 150 ps the device meets the needs of the most demanding clock applications.
Features www.
DataSheet4U.
com • 1:8 PLL based low-voltage clock generator LOW VOLTAGE 3.
3V LVCMOS 1:8 PLL CLOCK GENERATOR Freescale Semiconductor, Inc.
.
.
Pin and function compatible to the MPC953 FA SUFFIX Functional Description 32 LEAD LQFP PACKAGE The MPC9653 utilizes PLL technology to frequency lock its outputs CASE 873A onto an input reference clock.
Normal operation of the MPC9653 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback).
With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.
5 MHz or 50 to 125 MHz.
The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency.
Both must be selected to match the VCO frequency range.
The internal VCO of the MPC9653 is running at either 4x or 8x of the reference clock frequency.
The MPC9653 has a differential LVPECL reference input along with an external feedback input.
The device is ideal for use as a zero delay, low skew fanout buffer.
The device performance has been tuned and optimized for zero delay performance.
The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis.
In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs.
The PLL byp...

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