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IP2003APBF

International Rectifier
Part Number IP2003APBF
Manufacturer International Rectifier
Description Synchronous Buck Multiphase Optimized LGA Power Block Intergrated Power Semiconductors
Published Jul 10, 2008
Detailed Description PD-97051A iP2003APbF Synchronous Buck Multiphase Optimized LGA Power Block Features: Full function multiphase building ...
Datasheet PDF File IP2003APBF PDF File

IP2003APBF
IP2003APBF


Overview
PD-97051A iP2003APbF Synchronous Buck Multiphase Optimized LGA Power Block Features: Full function multiphase building block Output current 40A continuous with no derating up to TPCB = 100°C and TCASE = 100°C • Operating frequency up to 1.
0 MHz www.
DataSheet4U.
com • Proprietary packaging enables ultra low Rthj-case top • Efficient dual sided cooling • Small footprint low profile (9mm x11mm x 2.
2mm) package • Optimized for very low power losses • LGA interface • Ease of design Description The iP2003APbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.
2mm power block.
The only additional components required for a complete multiphase converter are a PWM controller, the output inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities.
iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality.
iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection.
Pin # 1 • • Integrated Power Semiconductors, Drivers & Passives iP2003APbF Power Block iP2003APbF Internal Block Diagram VSWS1 VSWS2 Pin N am e Pin Function V DD Supply voltage for the internal circuitry.
2 ENA BLE W hen set to logic level high, internal circuitry of the device is enabled.
W hen set to logic level low, the PRD Y pin is forced low, the Control and Sychronous switches are turned off, and the supply current reduces to 10µ A.
T T L-level input signal to M OSFET drivers.
Power Ready - This pin indicates the status of EN AB LE or V D D .
T his output will be driven low when EN ABLE is logic low or when V D D is less than 4.
4V (typ.
).
W hen EN AB ...



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