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IS61NLP25618A

Part Number	IS61NLP25618A
Manufacturer	ISSI
Description	(IS61NVPxxxxxA) STATE BUS SRAM
Published	Jul 12, 2008
Detailed Description	IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE ...
Datasheet	IS61NLP25618A PDF File

Overview

IS61NLP12832A IS61NLP12836A/IS61NVP12836A IS61NLP25618A/IS61NVP25618A 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI ® PRELIMINARY INFORMATION SEPTEMBER 2005 FEATURES www.
DataSheet4U.
com DESCRIPTION The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.
They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.
This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input.
Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH.
In this state the internal device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV input.
When the ADV is HIGH the internal burst counter is incremented.
New external addresses can be loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst sequence.
When tied HIGH, the interleaved burst sequence is selected.
When tied LOW, the linear burst sequence is selected.
• 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple de...

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IS61NLP25618A (IS61NVPxxxxxA) STATE BUS SRAM - ISSI

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