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CY7C1425JV18

Part Number	CY7C1425JV18
Manufacturer	Cypress Semiconductor
Description	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
Published	Jul 23, 2008
Detailed Description	CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Config...
Datasheet	CY7C1425JV18 PDF File

Overview

CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Configurations CY7C1410JV18 – 4M x 8 CY7C1425JV18 – 4M x 9 CY7C1412JV18 – 2M x 18 CY7C1414JV18 – 1M x 36 Separate independent read and write data ports ❐ Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz ■ ■ ■ Double Data Rate (DDR) interfaces on both read and write ports www.
DataSheet4U.
com ■ Functional Description The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.
8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.
QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.
The read port has data outputs to support read operations and the write port has data inputs to support write operations.
QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices.
Access to each port is accomplished through a common address bus.
The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock.
Accesses to the QDR-II read and write ports are completely independent of one another.
To maximize data throughput, both read and write ports are provided with DDR interfaces.
Each address location is associated with two 8-bit words (CY7C1410JV18), 9-bit words (CY7C1425JV18), 18-bit words (CY7C1412JV18), or 36-bit words (CY7C1414JV18) that burst sequentially into or out of the device.
Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which enables each port to operate independently.
All synchronous inputs pass through input r...

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CY7C1425JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture - Cypress Semiconductor

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