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CY7C1412AV18

Part Number	CY7C1412AV18
Manufacturer	Cypress Semiconductor
Description	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
Published	Jul 23, 2008
Detailed Description	CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • Separate ...
Datasheet	CY7C1412AV18 PDF File

Overview

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write www.
DataSheet4U.
com ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for bot...

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CY7C1412AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture - Cypress Semiconductor

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