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TC74HC590AF

Toshiba Semiconductor
Part Number TC74HC590AF
Manufacturer Toshiba Semiconductor
Description 8-Bit Binary Counter/Register
Published Aug 6, 2008
Detailed Description TC74HC590AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC590AP, TC74HC590AF 8-Bit Binary Counter/...
Datasheet PDF File TC74HC590AF PDF File

TC74HC590AF
TC74HC590AF

Overview
TC74HC590AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC590AP, TC74HC590AF 8-Bit Binary Counter/Register with 3-State Outputs The TC74HC590A is a high speed CMOS 8-BIT COUNTER/REGISTER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to epuivalent LSTTL while maintaining the CMOS low power dissipation.
The internal counter counts on the positive going edge of Counter Clock (CCK) when Counter Clock Enable ( CCKEN ) is low.
When Counter Clear ( CCLR ) is low, the internal counter is cleared asynchronously to the clock.
Data in the internal counter are loaded into the register at positive going edge of Register Clock (RCK), and the register outputs are controlled by enable input ( G ).
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features • High speed: fmax = 62 MHz (typ.
) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for RCO • Symmetrical output impedance: |IOH| = IOL = 6 mA (min) For QA to QH |IOH| = IOL = 4 mA (min) For RCO • Balanced propagation delays: tpLH ≈ tpHL • Wide operating voltage range: VCC (opr) = 2 to 6 V • Pin and function compatible with 74LS590 Pin Assignment TC74HC590AP TC74HC590AF Weight DIP16-P-300-2.
54A SOP16-P-300-1.
27A : 1.
00 g (typ.
) : 0.
18 g (typ.
) Start of commercial production 1988-05 1 2014-03-01 IEC Logic Symbol Block Diagram TC74HC590AP/AF Truth Table Inputs G RCK CCLR CCKEN CCK Function H X X X X Q Outputs Disable L X X X X Q Outputs Enable X X X X Counter Data is Stored into Register X X X X Register State is not Changed X X L X X Counter Clear X X H L Advance One Count X X H L No Count X X H H X No Count X: Don’t care RCO = QA′ ⋅ QB′ ⋅ QC′ ⋅ QD′ ⋅ QE′ ⋅ QF′ ⋅ QG′ ⋅ QH′ (QA’ to QH’: internal outputs of the counter) 2 201...


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