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N82C55A

Intel Corporation
Part Number N82C55A
Manufacturer Intel Corporation
Description CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Published Aug 16, 2008
Detailed Description 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Compatible with all Intel and Most Other Microprocessors High Speed ‘‘...
Datasheet PDF File N82C55A PDF File

N82C55A
N82C55A

Overview
82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Compatible with all Intel and Most Other Microprocessors High Speed ‘‘Zero Wait State’’ Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I O Pins Low Power CHMOS Completely TTL Compatible Y Y Y Control Word Read-Back Capability Direct Bit Set Reset Capability 2 5 mA DC Drive Capability on all I O Port Outputs Available in 40-Pin DIP and 44-Pin PLCC Available in EXPRESS Standard Temperature Range Extended Temperature Range Y Y Y Y Y Y The Intel 82C55A is a high-performance CHMOS version of the industry standard 8255A general purpose programmable I O device which is designed for use with all Intel and most other microprocessors It provides 24 I O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A-5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used www.
DataSheet4U.
com for handshaking and interrupt control signals MODE 2 is a strobed bi-directional bus configuration The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40-pin DIP and 44-pin plastic leaded chip carrier (PLCC) packages 231256 – 31 231256 – 1 Figure 1 82C55A Block Diagram 231256 – 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale October 1995 Order Number 231256-004 82C55A Table 1 Pin Description Symbol PA3–0 RD CS Pin Number Dip PLCC 1– 4 5 6 2–5 6 7 Type I O I I Name and Function PORT A PINS 0 – 3 Lower nibble of an 8-bit data output latch buffer and an 8-bit data input latch READ CONTROL This input is low during CPU read operations CHIP SELECT A low on this input enables the 82C55A to resp...


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