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79RC32435

Integrated Device Technology
Part Number 79RC32435
Manufacturer Integrated Device Technology
Description Communications Processor
Published Sep 19, 2008
Detailed Description IDTTM InterpriseTM Integrated Communications Processor 79RC32435 Device Overview The 79RC32435 is a member of the IDT™...
Datasheet PDF File 79RC32435 PDF File

79RC32435
79RC32435

Overview
IDTTM InterpriseTM Integrated Communications Processor 79RC32435 Device Overview The 79RC32435 is a member of the IDT™ Interprise™ family of PCI integrated communications processors.
It incorporates a high performance CPU core and a number of on-chip peripherals.
The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention, using a highly sophisticated direct memory access (DMA) engine.
All data transfers through the RC32435 are achieved by writing data from an on-chip I/O peripheral to main memory and then out to another I/O module.
Features x 32-bit CPU Core – MIPS32 instruction set – Cache Sizes: 8KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches – 16 dual-entry JTLB with variable page sizes – 3-entry instruction TLB – 3-entry data TLB – Max issue rate of one 32x16 multiply per clock – Max issue rate of one 32x32 multiply every other clock – CPU control with start, stop, and single stepping – Software breakpoints support – Hardware breakpoints on virtual addresses – ICE Interface that is compatible with v2.
5 of the EJTAG Specification x PCI Interface – 32-bit PCI revision 2.
2 compliant – Supports host or satellite operation in both master and target modes – Support for synchronous and asynchronous operation – PCI clock supports frequencies from 16 MHz to 66 MHz – PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitration – I2O “like” PCI Messaging Unit x Ethernet Interface – 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant – Supports MII or RMII PHY interface – Supports 64 entry hash table based multicast address filtering – 512 byte transmit and receive FIFOs – Supports flow control functions outlined in IEEE Std.
802.
3x1997 x DDR Memory Controller – Supports up to 256MB of DDR SDRAM – 1 chip select supporting 4 internal DDR banks – Supports a 16-bit wide data port using x8 or x16 bit wide DDR SDRAM devices – Suppor...


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