DatasheetsPDF.com

PLL102-109

Part Number	PLL102-109
Manufacturer	PhaseLink Corporation
Description	Programmable DDR Zero Delay Clock Driver
Published	Oct 28, 2008
Detailed Description	Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double D...
Datasheet	PLL102-109 PDF File

Overview

Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of six differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and CLK[T/C] from –0.
8ns to +3.
1ns by programming CLKINT and www.
DataSheet4U.
com FBOUT skew channel, or from –1.
1ns to +3.
5ns if additional DDR skew channels are enabled.
• Two independent programmable DDR skew channels from –0.
3ns to +0.
4ns with step size ± 100ps.
• Support 2-wire I 2 C serial bus interface.
• • 2.
5V Operating Voltage.
Available in 28-Pin 209mil SSOP.
• PIN ...

Similar Datasheet

PLL102-10 Low Skew Output Buffer - PhaseLink Corporation
PLL102-108 Programmable DDR Zero Delay Clock Driver - PhaseLink Corporation
PLL102-109 Programmable DDR Zero Delay Clock Driver - PhaseLink Corporation
PLL102-15 Low Skew Output Buffer - PhaseLink Corporation

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)