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IDT74ALVCH16903

Integrated Device Technology
Part Number IDT74ALVCH16903
Manufacturer Integrated Device Technology
Description 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER
Published Nov 10, 2008
Detailed Description IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BI...
Datasheet PDF File IDT74ALVCH16903 PDF File

IDT74ALVCH16903
IDT74ALVCH16903

Overview
IDT74ALVCH16903 3.
3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER INDUSTRIAL TEMPERATURE RANGE 3.
3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD • 0.
5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.
3V ± 0.
3V, Normal Range • VCC = 2.
7V to 3.
6V, Extended Range www.
DataSheet4U.
com • VCC = 2.
5V ± 0.
2V • CMOS power levels (0.
4µ W typ.
static) • Rail-to-Rail output swing for increased noise margin • Available in SSOP and TSSOP packages IDT74ALVCH16903 FEATURES: DESCRIPTION: DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND (Outputs Only) Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND –0.
5 to +4.
6 –0.
5 to VCC+0.
5 –65 to +150 –50 to +50 ±50 –50 ±100 Unit V V °C mA mA mA mA NOTES: 1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.
VCC terminals.
3.
This value is limited to 4.
6V maximum.
This 12-bit universal bus driver is built using advanced dual metal CMOS technology.
This device has dual outputs and can operate as a buffer or an edge-triggered register.
In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies.
The YERR output, which is produced one cycle after APAR, is open drain.
MODE selects one of the two data paths.
W...


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