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GS8161E32B

GSI Technology
Part Number GS8161E32B
Manufacturer GSI Technology
Description (GS8161E18B - GS8161E36B) Sync Burst SRAMs
Published Nov 17, 2008
Detailed Description GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT ...
Datasheet PDF File GS8161E32B PDF File

GS8161E32B
GS8161E32B

Overview
GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.
1 JTAG-compatible Boundary Scan • 2.
5 V or 3.
3 V +10%/–10% core power supply • 2.
5 V or 3.
3 V I/O supply www.
DataSheet4U.
com • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP and 165-bump BGA packages available 1M x 18, 512K x 36, 512K x 36 18Mb Sync Burst SRAMs 250 MHz–150 MHz 2.
5 V or 3.
3 V VDD 2.
5 V or 3.
3 V I/O Linear Burst Order (LBO) input.
The Burst function need not be used.
New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14).
Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
DCD Pipelined Reads The GS8161E18B(T/D)/GS8161E32B(D)/GS8161E36B(T/D) is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
SCD (Single Cycle Deselect) versions are also available.
DCD SRAMs pipeline disable commands to the same degree as read commands.
DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.
Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one...


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