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MPC940

Part Number	MPC940
Manufacturer	Motorola
Description	LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
Published	Nov 18, 2008
Detailed Description	MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Low Voltage 1:18 Clock Distribution Chip The MPC940 is a 1:1...
Datasheet	MPC940 PDF File

Overview

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information Low Voltage 1:18 Clock Distribution Chip The MPC940 is a 1:18 low voltage clock distribution chip.
The device features the capability to select either a differential LVPECL or an LVTTL/ LVCMOS compatible input.
The 18 outputs are LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines.
With output–to–output skews of 150ps, the MPC940 is ideal as a clock distribution chip for the most demanding of synchronous systems.
For a similar product with a larger number of www.
DataSheet4U.
com outputs, please consult the MPC941 data sheet.
MPC940 LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP • • • • • • LVPECL or LVCMOS/LVTTL Clock Input 150ps Maximum Targeted Output–to–Output Skew Drives Up to 36 Independent Clock Lines Maximum Output Frequency of 250MHz 32–Lead TQFP Packaging 3.
3V VCC Supply Voltage FA SUFFIX 32–LEAD TQFP PACKAGE CASE 873A–02 With a low output impedance (≈20Ω), in both the HIGH and LOW logic states, the output buffers of the MPC940 are ideal for driving series terminated transmission lines.
More specifically, each of the 18 MPC940 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC940 has an effective fanout of 1:36 in applications where each line drives a single load.
With this level of fanout, the MPC940 provides enough copies of low skew clocks for most high performance synchronous systems.
The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source.
The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies.
In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock.
A logic HIGH on th...

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