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MPC9229

Part Number	MPC9229
Manufacturer	Motorola
Description	400 MHz Low Voltage PECL Clock Synthesizer
Published	Oct 30, 2014
Detailed Description	MOTOROLA SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc. Order Number: MPC9229/D Rev 1 03/2003 400 MHz Lo...
Datasheet	MPC9229 PDF File

Overview

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc.
Order Number: MPC9229/D Rev 1 03/2003 400 MHz Low Voltage PECL Clock Synthesizer The MPC9229 is a 3.
3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications.
With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications.
MPC9229 400 MHZ LOW VOLTAGE CLOCK SYNTHESIZER Freescale Semiconductor, Inc.
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• • • • • • • • • • • • • Features 25 MHz to 400 MHz synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation 3.
3V power supply Fully integrated PLL Minimal frequency overshoot Serial 3-wire programming interface Parallel programming interface for power-up 32 lead LQFP and 28 PLCC packaging SiGe Technology Ambient temperature range 0°C to +70°C Pin and function compatible to the MC12429 FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference.
The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL.
The VCO within the PLL operates over a range of 800 to 1600 MHz.
Its output is scaled by a divider that is configured by either the serial or parallel interfaces.
The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal.
The PLL adjusts the VCO output frequency to be 4⋅M times the reference frequency by adjusting the VCO control voltage.
Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specif...

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