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MPC941

Part Number	MPC941
Manufacturer	Motorola
Description	LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP
Published	Nov 18, 2008
Detailed Description	MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Low Voltage 1:27 Clock Distribution Chip The MPC941 is a 1:27 l...
Datasheet	MPC941 PDF File

Overview

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview Low Voltage 1:27 Clock Distribution Chip The MPC941 is a 1:27 low voltage clock distribution chip.
The device features the capability to select either a differential LVPECL or an LVTTL/ LVCMOS compatible input.
The 27 outputs are LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines.
With output–to–output skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems.
For a similar product with a smaller number of www.
DataSheet4U.
com outputs, please consult the MPC940 data sheet.
MPC941 LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP • • • • • • • LVPECL or LVCMOS/LVTTL Clock Input 250ps Maximum Targeted Output–to–Output Skew Drives Up to 54 Independent Clock Lines Maximum Output Frequency of 250MHz High Impedance Output Enable 52–Lead TQFP Packaging 3.
3V VCC Supply Voltage FA SUFFIX With a low output impedance, in both the HIGH and LOW logic states, 52–LEAD TQFP PACKAGE the output buffers of the MPC941 are ideal for driving series terminated CASE 848D–03 transmission lines.
More specifically, each of the 27 MPC941 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC941 has an effective fanout of 1:54 in applications where each line drives a single load.
With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface directly with a LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source.
The LVCMOS/LVTTL input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies.
In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system cloc...

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