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LH28F800BGH-L

Sharp Electrionic Components
Part Number LH28F800BGH-L
Manufacturer Sharp Electrionic Components
Description 8 M-bit (512 kB x 16) SmartVoltage Flash Memories
Published Mar 22, 2005
Detailed Description LH28F800BG-L/BGH-L (FOR TSOP, CSP) LH28F800BG-L/BGH-L (FOR TSOP, CSP) DESCRIPTION The LH28F800BG-L/BGH-L flash memories...
Datasheet PDF File LH28F800BGH-L PDF File

LH28F800BGH-L
LH28F800BGH-L

Overview
LH28F800BG-L/BGH-L (FOR TSOP, CSP) LH28F800BG-L/BGH-L (FOR TSOP, CSP) DESCRIPTION The LH28F800BG-L/BGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications.
The LH28F800BG-L/BGH-L can operate at VCC = 2.
7 V and VPP = 2.
7 V.
Their low voltage operation capability realizes longer battery life and suits for cellular phone application.
Their boot, parameter and main-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for portable terminals and personal computers.
Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications.
For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BG-L/BGH-L offer two levels of protection : absolute protection with VPP at GND, selective hardware boot block locking.
These alternatives give designers ultimate control of their code security needs.
8 M-bit (512 kB x 16) SmartVoltage Flash Memories FEATURES • SmartVoltage technology – 2.
7 V, 3.
3 V or 5 V VCC – 2.
7 V, 3.
3 V, 5 V or 12 V VPP • High performance read access time LH28F800BG-L85/BGH-L85 – 85 ns (5.
0±0.
25 V)/90 ns (5.
0±0.
5 V)/ 100 ns (3.
3±0.
3 V)/120 ns (2.
7 to 3.
6 V) LH28F800BG-L12/BGH-L12 – 120 ns (5.
0±0.
5 V)/130 ns (3.
3±0.
3 V)/ 150 ns (2.
7 to 3.
6 V) • Enhanced automated suspend options – Word write suspend to read – Block erase suspend to word write – Block erase suspend to read • Enhanced data protection features – Absolute protection with VPP = GND – Block erase/word write lockout during power transitions – Boot blocks protection with WP# = VIL • SRAM-compatible write interface • Optimized array blocking architecture – Two 4 k-word boot blocks – Six 4 k-word parameter blocks – Fifteen 32 k-word main blocks – Top or bottom boot location • Enhanced cycling capability – 100 000 block erase cy...


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