DatasheetsPDF.com

MS8104160A

Part Number	MS8104160A
Manufacturer	OKI electronic componets
Description	Dual FIFO
Published	Nov 29, 2008
Detailed Description	OKI Semiconductor MS8104160A Dual FIFO (262,214 Words × 8 Bits) × 2 FEDS8104160A-01 This version: Nov. 21, 2002 GENERA...
Datasheet	MS8104160A PDF File

Overview

OKI Semiconductor MS8104160A Dual FIFO (262,214 Words × 8 Bits) × 2 FEDS8104160A-01 This version: Nov.
21, 2002 GENERAL DESCRIPTION The MS8104160A is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO (First-In First-Out) memories which were designed for 262,214 x 8-bit high-speed asynchronous read/write operation.
www.
DataSheet4U.
com The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in common.
The MS8104160A, functionally compatible with Oki's 2Mb FIFO memory (MSM518222A), can be used as a x16 configuration FIFO.
The MS8104160A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems.
The MS8104160A provides independent control clocks to support asynchronous read and write operations.
Different clock rates are also supported, which allow alternate data rates between write and read data streams.
The MS8104160A provides high speed FIFO (First-in First-out) operation without external refreshing: MS8104160A refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on.
Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.
The MS8104160A’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing.
The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 71 x 16-bit enable high speed first-bit-access...

Similar Datasheet

MS8104160 Dual FIFO - OKI electronic componets
MS8104160A Dual FIFO - OKI electronic componets
MS8104166 Dual FIFO - OKI electronic componets
MS8104166A Dual FIFO - OKI electronic componets

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)