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MCF5207

Freescale Semiconductor
Part Number MCF5207
Manufacturer Freescale Semiconductor
Description Microprocessor
Published Dec 4, 2008
Detailed Description www.DataSheet4U.com Freescale Semiconductor Data Sheet: Advance Information MCF5208EC Rev. 0.5, 3/2006 MCF5208 ColdFi...
Datasheet PDF File MCF5207 PDF File

MCF5207
MCF5207

Overview
www.
DataSheet4U.
com Freescale Semiconductor Data Sheet: Advance Information MCF5208EC Rev.
0.
5, 3/2006 MCF5208 ColdFire® Microprocessor Data Sheet Supports MCF5207 & MCF5208 by: Microcontroller Division The MCF5207 and MCF5208 devices are highly-integrated 32-bit microprocessors based on the version 2 ColdFire microarchitecture.
Both devices contain a 16-Kbyte internal SRAM, an 8-Kbyte configurable cache, a 2-bank SDR/DDR SDRAM controller, a 16-channel DMA controller, up to three UARTs, a queued SPI, a low-power management modeule, and other peripherals that enable the MCF5207 and MCF5208 for use in industrial control and connectivity applications.
The MCF5208 device also features a 10/100 Mbps fast ethernet controller.
This document provides detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF5207 and MCF5208 microprocessors.
It was written from the perspective of the MCF5208 device.
See the following section for a summary of differences between the two devices.
Table of Contents 1 2 3 4 5 6 MCF5207/8 Device Configurations.
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2 Ordering Information .
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3 Signal Descriptions.
3 Mechanicals and Pinouts .
8 Preliminary Electrical Characteristics .
18 Revision History .
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43 This document contains information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc.
, 2006.
All rights reserved.
• Preliminary www.
DataSheet4U.
com MCF5207/8 Device Configurations 1 MCF5207/8 Device Configurations Table 1.
MCF5207 & MCF5208 Configurations Module Version 2 ColdFire Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock ÷ 2) Performance (Dhrystone/2.
1 MIPS) Instruction/Data Cache Stat...


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