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AS7C33128PFS36B

Alliance Semiconductor Corporation
Part Number AS7C33128PFS36B
Manufacturer Alliance Semiconductor Corporation
Description (AS7C33128PFS32B / AS7C33128PFS36B) 3.3V 128K X 32/36 pipeline burst synchronous SRAM
Published Jan 1, 2009
Detailed Description March 2002 ® AS7C33128PFS32A AS7C33128PFS36A 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization...
Datasheet PDF File AS7C33128PFS36B PDF File

AS7C33128PFS36B
AS7C33128PFS36B

Overview
March 2002 ® AS7C33128PFS32A AS7C33128PFS36A 3.
3V 128K X 32/36 pipeline burst synchronous SRAM Features • Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LVCMOS • Fast clock to data access: 3.
0/3.
1/3.
5/4.
0/5.
0 ns • Fast OE access time: 3.
0/3.
1/3.
5/4.
0/5.
0 ns • Fully synchronous register-to-register operation • Single register “Flow-through” mode • Single-cycle deselect • Dual-cycle deselect also available (AS7C33128PFD32A/ www.
DataSheet4U.
com AS7C33128PFD36A) • Pentium®1 compatible architecture and timing • Asynchronous output enable control • • • • • • • Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.
3 core power supply 2.
5V or 3.
3V I/O operation with separate VDDQ 30 mW typical standby power in power down mode NTD™1 pipeline architecture available (AS7C33128NTD32A/ AS7C33128NTD36A) 1 Pentium® is a registered trademark of Intel Corporation.
NTD™ is a trademark of Alliance Semiconductor Corporation.
All trademarks mentioned in this document are the property of their respective owners.
Logic block diagram LBO CLK ADV ADSC ADSP A[16:0] 17 CLK CE CLR D Address CE register CLK D Q0 Burst logic Q1 17 Q Pin arrangement A6 A7 CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 128K × 32/36 Memory array 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 15 17 GWE BWE BWd DQd Q Byte write registers CLK D DQc Q Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK Q 36/32 36/32 BWc BWb BWa CE0 CE1 CE2 4 ZZ OE FT 36/32 DQ [a:d] Selection guide –200 Minimum cycle time Maximum clock frequency Maximum pipelined clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3 570 160 30 –183 5.
4 183 3.
1 540 140 30 –166 6 166 3.
5 475 130 30 –133 7.
5 133 4 425 100 30 –100 10 100 5 325 90 30 Units ns MHz ns mA...


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