DatasheetsPDF.com

IDT70V631S

IDT
Part Number IDT70V631S
Manufacturer IDT
Description HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
Published Jan 6, 2009
Detailed Description HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM True Dual-Port memory cells which allow simultaneous access ...
Datasheet PDF File IDT70V631S PDF File

IDT70V631S
IDT70V631S

Overview
HIGH-SPEED 3.
3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed access – Commercial: 10/12/15ns (max.
) – Industrial: 12ns (max.
) ◆ Dual chip enables allow for depth expansion without www.
DataSheet4U.
com external logic ◆ IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device ◆ M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ Busy and Interrupt Flags ◆ On-chip port arbitration logic ◆ Full on-chip hardware support of semaphore signaling between ports ◆ IDT70V631S Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Supports JTAG features compliant to IEEE 1149.
1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package.
LVTTL-compatible, single 3.
3V (±150mV) power supply for core LVTTL-compatible, selectable 3.
3V (±150mV)/2.
5V (±100mV) power supply for I/Os and control signals on each port Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram UBL LBL UBR LBR R/ WL B E 0 L B E 1 L B E 1 R B E 0 R R/WR CE0L CE1L CE0 R CE1 R OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R OER 256K x 18 MEMORY ARRAY I/O0L- I/O17L Din_L Din_R I/O0R - I/O17R A17L A0L Address Decoder ADDR_L ADDR_R Address Decoder A17R A0R OEL CE0L CE1L R/WL BUSYL SEML INTL ARBITRATION INTERRUPT SEMAPHORE LOGIC OER CE0 R CE1 R R/WR BUSYR M/ S SEM R INTR TDI TDO JTAG TMS TCK TRST 5622 drw 01 NOTES: 1.
BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2.
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2003 DSC-5622/5 1 ©2003 Integrated Device Technology, Inc.
IDT70...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)