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K7N403601M

Samsung semiconductor
Part Number K7N403601M
Manufacturer Samsung semiconductor
Description (K7N401801M / K7N403601M) 128Kx36 & 256Kx18 Pipelined NtRAM-TM
Published Jan 25, 2009
Detailed Description K7N403601M K7N401801M www.DataSheet4U.com 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pip...
Datasheet PDF File K7N403601M PDF File

K7N403601M
K7N403601M

Overview
K7N403601M K7N401801M www.
DataSheet4U.
com 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History Rev.
No.
0.
0 0.
1 History 1.
Initial document.
1.
Changed tCD,tOE from 4.
0ns to 4.
2ns at -75 2.
Changed DC condition at Icc and parameters ISB1 ; from 10mA to 30mA, ISB2 ; from 10mA to 30mA.
Add VDDQ Supply voltage( 2.
5V I/O ) Changed VOL Max value from 0.
2V to 0.
4V at 2.
5V I/O.
Final spec Release.
Remove VDDQ Supply voltage( 2.
5V I/O ) Add VDDQ Supply voltage( 2.
5V I/O ) Draft Date July.
06.
1998 Oct.
10 .
1998 Remark Preliminary Preliminary 0.
2 0.
3 1.
0 2.
0 3.
0 Dec.
10.
1998 Dec.
23.
1998 Jan.
29.
1999 Feb.
25.
1999 May.
13.
1999 Preliminary Preliminary Final Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics.
SAMSUNG Electronics CO.
, LTD.
reserve the right to change the specifications.
SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device.
If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1- May 1999 Rev 3.
0 K7N403601M K7N401801M www.
DataSheet4U.
com 128Kx36 & 256Kx18 Pipelined NtRAMTM 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM GENERAL DESCRIPTION The K7N403601M and K7N401801M are 4,718,592 bits Synchronous Static SRAMs.
The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising edge of the clock input.
This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incomming signals.
For read cycles, pipelined SR...


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