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HY5DU561622CTP

Part Number	HY5DU561622CTP
Manufacturer	Hynix
Description	256M gDDR SDRAM
Published	Feb 25, 2009
Detailed Description	www.DataSheet4U.com HY5DU561622CTP 256M(16Mx16) gDDR SDRAM HY5DU561622CTP This document is a general product descripti...
Datasheet	HY5DU561622CTP PDF File

Overview

www.
DataSheet4U.
com HY5DU561622CTP 256M(16Mx16) gDDR SDRAM HY5DU561622CTP This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
5 / Feb.
2006 1 1HY5DU561622CTP www.
DataSheet4U.
com Revision History Revision No.
0.
1 0.
2 0.
3 0.
4 0.
5 History Defined target spec.
Supports Pb free parts for each speed grade Insert AC Overshoot comment tRAS_max change tRAS_min & tQHS change Draft Date Aug.
2003 Sep.
2003 Aug.
2004 Sep.
2004 Oct.
2004 Remark Rev.
0.
5 / Feb.
2006 2 1HY5DU561622CTP www.
DataSheet4U.
com PRELIMINARY DESCRIPTION The Hynix HY5DU561622CTP is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.
FEATURES • • • • • • • • • • 2.
5V +/-5% VDD and VDDQ power supply supports 250 / 200 / 166MHz 2.
6V VDD/VDDQ wide range min/max power supply supports 300/275Mhz 2.
8V +/-0.
1V VDD and VDDQ power supply supports 350MHz All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.
65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (c...

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