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ASM3P2508SP

Alliance Semiconductor Corporation
Part Number ASM3P2508SP
Manufacturer Alliance Semiconductor Corporation
Description Clock Synthesizer and Frequency Generator
Published Mar 3, 2009
Detailed Description February 2005 www.DataSheet4U.com rev 0.4 ASM3P2508SP Clock Synthesizer and Frequency Generator with Peak EMI reductio...
Datasheet PDF File ASM3P2508SP PDF File

ASM3P2508SP
ASM3P2508SP

Overview
February 2005 www.
DataSheet4U.
com rev 0.
4 ASM3P2508SP Clock Synthesizer and Frequency Generator with Peak EMI reduction Features ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ Dual PLL based Architecture Operates with a 3.
3V ±0.
3V supply.
Generates an EMI optimized Spread Spectrum PCI Clock output Generates a high accuracy non Spread T1 clock of ±25ppm accuracy.
Generates a non spread system reference clock Low power CMOS design.
Input frequency: 25 MHz.
Outputs: Sys_ REF_CLK: 20 MHz T1 Clock: 25 MHz (±25 ppm) PCI_CLK: 33.
33MHz Spread Spectrum ƒ Frequency deviation: -0.
5% (Typ).
Available in 8L SOIC Package.
The ASM3P2508SP uses the most efficient and optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics.
This results in a significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’ (SSCG).
In addition to the SSCG output, ASM3P2508SP generates two high accuracy clock signals T1 Clock @ 25.
00MHz with +/- 25ppm stability, and a 20MHz Sys_ REF_CLK.
ƒ Applications The ASM3P2508SP is targeted towards Consumer, Industrial, Data and Telecommunications applications.
Product Description The ASM3P2508SP is a versatile Dual PLL based Clock Synthesizer and Frequency Generator optimised and designed specifically for three clock frequencies.
The PCI_CLK output from ASM3P2508SP reduces Key Specifications Description Supply voltages Input Frequency Cycle-to-Cycle Jitter Output Duty Cycle Output Rise and Fall Time SSC Modulation Rate SSC Frequency Deviation Specification VDD = 3.
3V ±0.
3V 25 MHz 175 pS ( Max) 45/55% 1.
1 nS (Max) 30KHz (Typ) -0.
5% (Typ) electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of all clock dependent signals.
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