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MT8920B

Mitel Networks Corporation
Part Number MT8920B
Manufacturer Mitel Networks Corporation
Description ST-BUS Parallel Access Circuit
Published May 22, 2009
Detailed Description ® ISO-CMOS ST-BUS™ FAMILY MT8920B ST-BUS Parallel Access Circuit www.datasheet4u.com Features • • • • • High speed pa...
Datasheet PDF File MT8920B PDF File

MT8920B
MT8920B

Overview
® ISO-CMOS ST-BUS™ FAMILY MT8920B ST-BUS Parallel Access Circuit www.
datasheet4u.
com Features • • • • • High speed parallel access to the serial ST-BUS Parallel bus optimized for 68000 µP (mode 1) Fast dual-port RAM access (mode 2) Access time: 120 nsec Parallel bus controller (mode 3) - no external controller required Flexible interrupt capabilities - two independent/programmable interrupt sources with auto-vectoring Selectable 24 and 32 channel operation Programmable loop-around modes Low power CMOS technology ISSUE 6 June 1996 Ordering Information MT8920BE 28 Pin Plastic DIP MT8920BC 28 Pin Ceramic DIP MT8920BP 28 Pin Plastic J-Lead MT8920BS 28 Pin SOIC -40°C to 85°C Description The ST-BUS Parallel Access Circuit (STPA) provides a simple interface between Mitel’s ST-BUS and parallel system environments.
• • • Applications • • • • • Parallel control/data access to T1/CEPT digital trunk interfaces Digital signal processor interface to ST-BUS Computer to Digital PABX link Voice store and forward systems Interprocessor communications D7-D0 A4-A0 Tx0 Dual Port Ram 32 X 8 Parallelto-serial Converter STo0 CS DS, OE R/W, WE DTACK, BUSY, DCS IRQ, 24/32 IACK, MS1 A5, STCH MMS Rx0 Dual Port Ram 32 X 8 Parallel Port Interface Interrupt Registers Control Registers Serial-toParallel Converter STi0 Tx1 Dual Port Ram 32 X 8 Parallelto-Serial Converter Comp/ MUX Address Generator STo1 F0i C4i VSS VDD Figure 1 - Functional Block Diagram 3-3 3 MT8920B CMOS STi0 IACK, MS1 F0i C4i VDD MMS DTACK, BUSY, DCS 4 3 2 1 28 27 26 • 28 PIN PDIP/CERDIP/SOIC Figure 2 - Pin Connections Pin Description Pin # 1 2 Name C4i F0i Description‡ 4.
096 MHz Clock.
The ST-BUS timing clock used to establish bit cell boundaries for the serial bus.
Framing Pulse.
A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS stream.
The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of a frame.
Interrupt Acknowledge (Mode 1).
This activ...


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