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LTC2202

Linear Technology
Part Number LTC2202
Manufacturer Linear Technology
Description 25Msps/10Msps ADCs
Published May 26, 2009
Detailed Description LTC2203/LTC2202 16-Bit, 25Msps/10Msps ADCs FEATURES n Sample Rate: 25Msps/10Msps n 81.6dB SNR and 100dB SFDR (2.5V Rang...
Datasheet PDF File LTC2202 PDF File

LTC2202
LTC2202

Overview
LTC2203/LTC2202 16-Bit, 25Msps/10Msps ADCs FEATURES n Sample Rate: 25Msps/10Msps n 81.
6dB SNR and 100dB SFDR (2.
5V Range) n SFDR 90dB at 70MHz (1.
667VP-P Input Range) n PGA Front End (2.
5VP-P or 1.
667VP-P Input Range) n 380MHz Full Power Bandwidth S/H n Optional Internal Dither n Optional Data Output Randomizer n Single 3.
3V Supply n Power Dissipation: 220mW/140mW n Clock Duty Cycle Stabilizer n Out-of-Range Indicator n Pin Compatible Family 25Msps: LTC2203 (16-Bit) 10Msps: LTC2202 (16-Bit) n 48-Pin (7mm × 7mm) QFN Package APPLICATIONS n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE DESCRIPTION The LTC®2203/LTC2202 are 25Msps/10Msps, sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 380MHz.
The input range of the ADC can be optimized with the PGA front end.
The LTC2203/LTC2202 are perfect for demanding applications, with AC performance that includes 81.
6dB SNR and 100dB spurious free dynamic range (SFDR).
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes).
A separate output power supply allows the CMOS output swing to range from 0.
5V to 3.
6V.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.
S.
Patents including 4843302, 6949965B1.
TYPICAL APPLICATION VCM 2.
2μF 1.
25V COMMON MODE BIAS VOLTAGE AIN + ANALOG INPUT AIN – + S/H AMP – CLOCK/DUTY CYCLE CONTROL CLK 3.
3V SENSE INTERNAL ADC REFERENCE GENERATOR OVDD 16-BIT PIPELINED ADC CORE CORRECTION LOGIC AND SHIFT REGISTER OUTPUT DRIVERS OGND VDD GND PGA SHDN DITH MODE OE ADC CONTROL INPUTS RAND 0.
5V TO 3.
6V 1μF OF CLKOUT+ CLKOUT– D15 • • • D0 CMOS O...


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