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NJU7007

JRC
Part Number NJU7007
Manufacturer JRC
Description LOW POWER AND LOW OFFSET VOLTAGE SUPER SMALL-SIZED SINGLE C-MOS OPERATIONAL AMPLIFIER
Published Jun 13, 2009
Detailed Description NJU7007/08 LOW POWER AND LOW OFFSET VOLTAGE SUPER SMALL-SIZED SINGLE C-MOS OPERATIONAL AMPLIFIER ■GENERAL DESCRIPTION ...
Datasheet PDF File NJU7007 PDF File

NJU7007
NJU7007

Overview
NJU7007/08 LOW POWER AND LOW OFFSET VOLTAGE SUPER SMALL-SIZED SINGLE C-MOS OPERATIONAL AMPLIFIER ■GENERAL DESCRIPTION The NJU7007/08 are super small-sized package single C-MOS operational amplifiers operated on a single-powersupply, low power, low offset voltage and low operating current.
The input offset voltage is lower than 4mV, and the input bias current is as low as than 1pA, consequently very small signal around the ground level can be amplified.
The minimum operating voltage is 1V and the output stage permits output signal to swing between both of the supply rails.
Furthermore, The NJU7007/08 are packaged with super small-sized SC88A, therefore it can be especially applied to portable items.
■PACKAGE INFORMATION NJU7007F3 NJU7008F3 ■FEATURES ●Low Offset Voltage ●Single Low Power Supply ●Wide Output Swing Range ●Low Operating Current VIO=4mV max VDD=1.
0~5.
5V VOM=2.
9V min @ VDD=3.
0V (See Line-up) ●Low Bias Current IIB=1pA typ ●Compensation Capacitor Incorporated ●Package Outline SC88A ●C-MOS Technology ■PIN CONFIGURATION (Top View) IN+ 1 5 VDD VSS 2 IN- 3 4 OUT ■LINE-UP PARAMETER Operating Current Slew Rate Unity Gain Bandwidth NJU7007 15 0.
1 0.
2 (VDD=3.
0V,Ta=25C) NJU7008 UNIT 200 μA(typ) 2.
4 V/μs(typ) 1.
0 MHz(typ) ■EQUIVALENT CIRCUIT VDD INOUT IN+ VSS 10/2/2018 ( 1 / 4 ) NJU7007/08 ■ABSOLUTE MAXIMUM RATINGS (Ta=25C) PARAMETER SYMBOL RATING UNIT Supply Voltage Differential Input Voltage Common Mode Input Voltage Power Dissipation Operating Temperature VDD VID VIC PD Topr 7.
0 ±7.
0 (Note1) -0.
3~7.
0 250 (Note2) -40~+85 V V V mW °C Storage Temperature Tstg -55~+125 °C Note1) If the supply voltage (VDD) is less than 7.
0V, the input voltage must not over the VDD level though 7.
0V is limit specified.
Note2) The power dissipation is value mounted on a glass epoxy board (FR-4) in size of 114.
3x76.
2x1.
6 mm.
Note3) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for the circuit.
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