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PTN3360A

NXP
Part Number PTN3360A
Manufacturer NXP
Description Enhanced Performance HDMI/DVI Level Shifter
Published Jun 22, 2009
Detailed Description www.DataSheet4U.com PTN3360A Enhanced performance HDMI/DVI level shifter with inverting HPD Rev. 01 — 4 May 2009 Produc...
Datasheet PDF File PTN3360A PDF File

PTN3360A
PTN3360A

Overview
www.
DataSheet4U.
com PTN3360A Enhanced performance HDMI/DVI level shifter with inverting HPD Rev.
01 — 4 May 2009 Product data sheet 1.
General description The PTN3360A is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.
0 and HDMI v1.
3a compliant open-drain current-steering differential output signals, up to 2.
5 Gbit/s per lane.
Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.
3 V on the sink side.
Additionally, the PTN3360A provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 1.
1 V on the source side and provides a channel for level shifting of the DDC channel (consisting of a clock and a data line) between 3.
3 V source-side and 5 V sink-side.
The DDC channel is implemented using pass-gate technology providing level shifting as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3360A typically come from a display source with multi-mode I/O, which supports multiple display standards, e.
g.
, DisplayPort, HDMI and DVI.
While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.
0 or HDMI v1.
3a specification.
By using PTN3360A, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low.
See Figure 1.
The PTN3360A main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.
1 and/or PCI Express Standard v1.
1, and open-drain current-steeri...


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