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ADCLK846

Part Number	ADCLK846
Manufacturer	Analog Devices
Description	6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer
Published	Jul 1, 2009
Detailed Description	www.DataSheet4U.com 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846 FUNCTIONAL BLOCK DIAGRAM ADCLK...
Datasheet	ADCLK846 PDF File

Overview

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DataSheet4U.
com 1.
8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer ADCLK846 FUNCTIONAL BLOCK DIAGRAM ADCLK846 LVDS/CMOS OUT0 (OUT0A) OUT0 (OUT0B) VREF OUT1 (OUT1A) CLK CLK CTRL_A LVDS/CMOS OUT2 (OUT2A) OUT2 (OUT2B) OUT3 (OUT3A) OUT3 (OUT3B) OUT4 (OUT4A) CTRL_B SLEEP OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) 07226-001 FEATURES Selectable LVDS/CMOS outputs Up to 6 LVDS (1.
2 GHz) or 12 CMOS (250 MHz) outputs <16 mW per channel (100 MHz operation) 54 fs integrated jitter (12 kHz to 20 MHz) 100 fs additive broadband jitter 2.
0 ns propagation delay (LVDS) 135 ps output rise/fall (LVDS) 65 ps output-to-output skew (LVDS) Sleep mode Pin-programmable control 1.
8 V power supply OUT1 (OUT1B) APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation Figure 1.
GENERAL DESCRIPTION The ADCLK846 is a 1.
2 GHz/250 MHz, LVDS/CMOS, fanout...

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