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LF3304

Part Number	LF3304
Manufacturer	LOGIC Devices Incorporated
Description	Dual Line Buffer/FIFO
Published	Mar 22, 2005
Detailed Description	LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO DESCRIPTION The ...
Datasheet	LF3304 PDF File

Overview

LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO DESCRIPTION The LF3304 is a dual line buffer/ FIFO, designed to operate at HDTV rates.
The LF3304 will operate in two distinct modes: Line Buffer and FIFO.
In these modes the two memories can operate independently or with common control.
The LF3304 comprises two 12-bit 4K memories configurable in a variety of ways including: Two 12-bit 4K deep line buffers (independent lengths), Three 8-bit 4K deep line buffers (common lengths), One 12-bit 8K deep line buffer, or Two 12-bit 4K FIFOs (independent operation).
In FIFO mode, independent Read and Write Resets give the designer control over the internal pointers providing flexibility not commonly found in ordinary FIFOs.
The LF3304 operatates at a maximum data rate of 100 MHz and is available in a 100-lead PQFP package.
FEATURES u 100 MHz Data Rate for Video and other High-Speed Applications u One 24-bit, Two 12-bit, Three 8-bit Data Paths, or One Double Depth 12-bit u Dual Modes: Line Buffer or FIFO u User-Programmable FIFO Flags u User-Resettable Read and Write Pointers u Single 3.
3 V Power Supply, 5 V Tolerant I/O u 100-lead PQFP LF3304 BLOCK DIAGRAM WCLKA RCLKA WENA RENA RRA RWA RAM ARRAY 1 CONTROL FLAG GENERATOR FFA EFA PAFA PAEA OEA 12 AIN11-0 VARIABLE LENGTH RAM ARRAY A 4K x 12-bit 12 AOUT11-0 ADDRA LDA 12 LENGTH11-0 ADDRB LDB MASTER CONTROL VARIABLE LENGTH RAM ARRAY B 12 BIN11-0 12 BOUT11-0 4K x 12-bit OEB 2 MODE1-0 WCLKB RCLKB WENB RENB RRB RWB RAM ARRAY 2 CONTROL FLAG GENERATOR FFB EFB PAFB PAEB Video Imaging Products 1 08/16/2000–LDS.
3304-F LF3304 DEVICES INCORPORATED Dual Line Buffer/FIFO the data presented on LENGTH11-0 is loaded into the device on the active edge of WCLKA in conjunction with LDA being driven LOW.
To set the length of RAM Array B the data presented on LENGTH11-0 is loaded into the device on the active edge of WCLKB in conjunction with LDB being driven LOW.
If an equal ...

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