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STLS2F02

STMicroelectronics
Part Number STLS2F02
Manufacturer STMicroelectronics
Description High performance 64-bit superscalar MIPS microprocessor
Published Jul 19, 2009
Detailed Description www.DataSheet4U.com STLS2F02 high performance 64-bit superscalar Features ■ ■ ■ ■ ■ ■ ■ MIPS® Loongson 2F microproces...
Datasheet PDF File STLS2F02 PDF File

STLS2F02
STLS2F02

Overview
www.
DataSheet4U.
com STLS2F02 high performance 64-bit superscalar Features ■ ■ ■ ■ ■ ■ ■ MIPS® Loongson 2F microprocessor Preliminary Data 64-bit superscalar architecture 900 MHz clock frequency Single/double precision floating-point units New streaming multimedia instruction set support (SIMD) 64 Kbyte instruction cache, 64 Kbyte data cache, on-chip 512 Kbyte unified L2 cache On chip DDR2-667 and PCI-X controller 4 W @ 900 MHz power consumption: – Best in class for power management – Voltage/frequency scaling – Standby mode support – L2 cache disable/enable option Leading edge 90 nm process technology 27x27 heat spreader flip-chip BGA package MIPS based (compatible with MIPSIII) instruction set HFCBGA452 (27x27x2.
9mm) The memory hierarchy is composed by the first level of 64 Kbyte 4-way set associative caches for instructions and data, the second level of 512 Kbyte unified 4-way set associative cache and the memory management unit with table lookside buffer.
The Loongson microprocessor family is the outcome of a successful collaboration started in 2004 between STMicroelectronics and the Institute of Computing Technology, part of the Chinese Academy of Science.
Loongson microprocessors were co-developed by STMicroelectronics and the Institute of Computing Technology to address all the applications requiring high level of performance and low power dissipation.
Compared to the STLS2E02 processor, the STLS2F02 has an enhanced architecture providing higher performances, reduced power consumption, integrated DDR2 memory controller and PCI-X bus interface.
■ ■ ■ Description The STLS2F02 is a MIPS based 64-bit superscalar microprocessor, able to issue four instructions per clock cycle among six functional units: two integer, two single/double-precision floating-point, one 64-bit SIMD and one load/store unit.
The micro architecture is organized with nine stages of pipeline and support of dynamic branch prediction.
Table 1.
Device summary Order code STLS2F02 Package H...


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