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GS9092A

Gennum Corporation
Part Number GS9092A
Manufacturer Gennum Corporation
Description GenLINX-R III 270Mb/s Serializer
Published Aug 16, 2009
Detailed Description www.DataSheet4U.com GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI GS9092A Data Sheet Key Features • • • ...
Datasheet PDF File GS9092A PDF File

GS9092A
GS9092A

Overview
www.
DataSheet4U.
com GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI GS9092A Data Sheet Key Features • • • • SMPTE 259M-C compliant scrambling and NRZI to NRZ encoding (with bypass) DVB-ASI sync word insertion and 8b/10b encoding Integrated Cable Driver Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet insertion, and ancillary data packet insertion User selectable additional processing features including: • • • • • • • • • • ANC data checksum, and line number calculation and insertion TRS and EDH packet generation and insertion illegal code remapping Description The GS9092A is a 270Mb/s serializer with an internal FIFO and an integrated cable driver.
It contains all the necessary blocks to realize a transmit solution for SD-SDI and DVB-ASI applications.
In addition to serializing the input data stream, the GS9092A performs NRZI-to-NRZ encoding and scrambling as per SMPTE 259M-C when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will insert K28.
5 sync characters and 8b/10b encode the data prior to serialization.
Parallel data inputs are provided for 10-bit multiplexed formats at SD signal rates.
A 27MHz parallel clock input signal is also required.
The integrated cable driver features an adjustable signal swing and common mode operating point offering fully compliant SMPTE 259M-C cable driver connectivity.
The GS9092A includes a range of data processing functions such as automatic standards detection and EDH support.
The device can also insert TRS signals, re-map illegal code words, and generate and insert SMPTE 352M payload identifier packets.
All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming.
The GS9092A also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to carry out tasks such as data delay, clock phase interchange, MPEG packet insertion and clock rate interchang...


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