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CY2SSTV850

Part Number	CY2SSTV850
Manufacturer	Cypress Semiconductor
Description	Differential Clock Buffer/Driver
Published	Jan 29, 2010
Detailed Description	STV850 CY2SSTV850 Differential Clock Buffer/Driver Features • Phase-locked loop clock distribution for Double Data Rat...
Datasheet	CY2SSTV850 PDF File

Overview

STV850 CY2SSTV850 Differential Clock Buffer/Driver Features • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications • 1:10 differential outputs • External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • SSCG: Spread Aware™ for EMI reduction • 48-pin SSOP and TSSOP packages • Conforms to JEDEC JC40 and JC42.
5 DDR specifications Description This PLL clock buffer is designed for 2.
5 VDD and 2.
5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and on...

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