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ICS91305

Integrated Circuit Systems
Part Number ICS91305
Manufacturer Integrated Circuit Systems
Description High Performance Communication Buffer
Published Feb 9, 2010
Detailed Description Integrated Circuit Systems, Inc. ICS91305 High Performance Communication Buffer General Description The ICS91305 is a ...
Datasheet PDF File ICS91305 PDF File

ICS91305
ICS91305

Overview
Integrated Circuit Systems, Inc.
ICS91305 High Performance Communication Buffer General Description The ICS91305 is a high performance, low skew, low jitter clock driver.
It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.
It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.
ICS91305 is a zero delay buffer that provides synchronization between the input and output.
The synchronization is established via CLKOUT feed back to the input of the PLL.
Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.
The ICS91305 comes in an eight pin 150 mil SOIC package.
It has five output clocks.
In the absence of REF input, will be in the power down mode.
In this mode, the PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption for a standby condition.
Features • • • ...


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