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NB7V33M

ON Semiconductor
Part Number NB7V33M
Manufacturer ON Semiconductor
Description 1.8V / 2.5V 10GHz Div By 4 Clock Divider
Published Feb 11, 2010
Detailed Description NB7V33M 1.8V / 2.5V, 10GHz ÷4 Clock Divider with CML Outputs Multi−Level Inputs w/ Internal Termination Description The ...
Datasheet PDF File NB7V33M PDF File

NB7V33M
NB7V33M

Overview
NB7V33M 1.
8V / 2.
5V, 10GHz ÷4 Clock Divider with CML Outputs Multi−Level Inputs w/ Internal Termination Description The NB7V33M is a differential B4 Clock divider with asynchronous reset.
The differential Clock inputs incorporate internal 50 W termination resistors and will accept LVPECL, CML and LVDS logic levels.
The NB7V33M produces a ÷4 output copy of an input Clock operating up to 10 GHz with minimal jitter.
The Reset pin is asserted on the rising edge.
Upon powerup, the internal flip*flops will attain a random state; the Reset allows for the synchronization of multiple NB7V33M’s in a system.
The 16 mA differential CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated with 50 W to VCC.
The NB7V33M is the B4 version of the NB7V32M (B2) and is offered in a low profile 3 mm x 3 mm 16−pin QFN package.
The NB7V33M is a member of the GigaComm™ family of high performance clock products.
Application notes, models, and support documentation are available at www.
onsemi.
com.
Features • Maximum Input Clock Frequency > 10 GHz, typical • 260 ps Typical Propagation Delay • 35 ps Typical Rise and Fall Times • Differential CML Outputs, 400 mV Peak−to−Peak, Typical • Operating Range: VCC = 1.
71 V to 2.
625 V with GND = 0 V • Internal 50 W Input Termination Resistors • Random Clock Jitter < 0.
8 ps RMS • QFN−16 Package, 3 mm x 3 mm • −40ºC to +85°C Ambient Operating Temperature • These are Pb−Free Devices http://onsemi.
com 1 QFN16 MN SUFFIX CASE 485G MARKING DIAGRAM* 16 1 NB7V 33M ALYW G G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
R VTCLK 50 W CLK CLK 50 W VTCLK RESET B4 Q0 Q0 VREFAC VCC GND Figure 1.
Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data...


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