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ispClock5406D

Part Number	ispClock5406D
Manufacturer	Lattice Semiconductor
Description	Zero Delay And Fan-Out Buffer
Published	Feb 11, 2010
Detailed Description	ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2...
Datasheet	ispClock5406D PDF File

Overview

ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2009 Preliminary Data Sheet DS1025 Features CleanClock™ PLL  Ultra Low Period Jitter 2.
5ps  Ultra Low Phase Jitter 6.
5ps  Fully Integrated High-Performance PLL • • • • • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Internal/external feedback  Up to 10 Programmable Fan-out Buffers • Programmable differential output standards and individual enable controls - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Up to 10 banks with individual VCCO and GND - 1.
5V, 1.
8V, 2.
5V, 3.
3V  All I/Os are Hot Socket Compliant  Operating Modes • Fan-out buffer with programmable output skew control • Zero delay buffer with dual programmable skew controls  Flexible Clock Reference and External Feedback Inputs • Programmable differential input reference/feedback standards - LVDS, LVPECL, HSTL, SSTL, HCSL, MLVDS • Programmable termination • Clock A/B selection multiplexer FlexiClock™ I/O  40 MHz to 400 MHz Input/Output Operation  Dual Programmable Skew Per Output • Programmable phase adjustment - 16 settings; minimum step size 156 ps - Up to +/- 9.
4 ns skew range - Coarse and fine adjustment modes • Programmable time delay adjustment - 16 settings; 18 ps www.
DataSheet4U.
com  Dynamic Reconfiguration through I2C  Full JTAG Boundary Scan Test In-System Programming Support  Exceptional Power Supply Noise Immunity  Commercial (0° to 70°C) and Industrial (-40° to 85°C) Temperature Ranges  48-Pin and 64-pin QFNS Packages  Applications • • • • Low-cost clock source for SERDES ATCA, MicroTCA, AMC, PCI Express Differential Clock Distribution Generic Source Synchronous Clock  Management • Zero-delay clock buffer  Dynamic Skew Control Through I2C  Low Output-to-Output Skew (<100ps) ispClock5400D Family Functional Diagram PLL_BYPASS I2C Interface REFSEL REFA REFB 0 1 Phase Freq.
Detect CleanClock ...

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