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MC100ES6056

Integrated Device Technology
Part Number MC100ES6056
Manufacturer Integrated Device Technology
Description ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
Published Feb 24, 2010
Detailed Description www.DataSheet4U.com 2.5V, 3.3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER The MC100ES6056 is a dual, fully diffe...
Datasheet PDF File MC100ES6056 PDF File

MC100ES6056
MC100ES6056

Overview
www.
DataSheet4U.
com 2.
5V, 3.
3V ECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER The MC100ES6056 is a dual, fully differential 2:1 multiplexer.
The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
Multiple VBB pins are provided.
The VBB pin, an internally generated voltage supply, is available to this device only.
For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs.
When used, decouple VBB and VCC via a 0.
01 µF capacitor and limit current sourcing or sinking to 0.
5 mA.
When not used, VBB should be left open.
The device features both individual and common select inputs to address both data path and random logic applications.
The 100ES Series contains temperature compensation.
Features • • • • • • • • • • 360 ps Typical Propagation Delays Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 2.
375 V to 3.
8 V with VEE = 0 V ECL Mode Operating Range: VCC = 0 V with VEE = –2.
375 V to –3.
8 V Open Input Default State Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs LVDS Input Compatible 20-Lead Pb-Free Package Available MC100ES6056 DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-03 EJ SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948E-03 EG SUFFIX 20-LEAD SOIC PACKAGE Pb-FREE PACKAGE CASE 751D-07 ORDERING INFORMATION Device MC100ES6056DT MC100ES6056DTR2 MC100ES6056EJ MC100ES6056EJR2 MC100ES6056EG MC100ES6056EGR2 Package TSSOP-20 TSSOP-20 TSSOP-20 (Pb-Free) TSSOP-20 (Pb-Free) SOIC-20 (Pb-Free) SOIC-20 (Pb-Free) VCC 20 Q0 19 Q0 18 SEL0 COM_SEL SEL1 17 16 15 VCC 14 Q1 13 Q1 12 VEE 11 1 0 1 0 1 D0a 2 D0a 3 VBB0 4 D0b 5 D0b 6 D1a 7 D1a 8 VBB1 9 D1b 10 D1b Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1.
20-Lead Pinout (Top View) and Logic Diagram IDT™ / ICS™ 2:1 MU...


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