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HYMD232M726AJ8-H

Part Number	HYMD232M726AJ8-H
Manufacturer	Hynix Semiconductor
Description	Unbuffered DDR SO-DIMM
Published	Mar 16, 2010
Detailed Description	32Mx72 bits Unbuffered DDR SO-DIMM HYMD232M726A(L)8-J/M/K/H/L DESCRIPTION Hynix HYMD232M726A(L)8-J/M/K/H/L series is unb...
Datasheet	HYMD232M726AJ8-H PDF File

Overview

32Mx72 bits Unbuffered DDR SO-DIMM HYMD232M726A(L)8-J/M/K/H/L DESCRIPTION Hynix HYMD232M726A(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx72 high-speed memory arrays.
Hynix HYMD232M726A(L)8-J/M/K/H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate.
Hynix HYMD232M726A(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs.
While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2.
High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence detect).
Serial presence detect function is implemented via a serial 2,048-bit EEPROM.
The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
www.
DataSheet4U.
com FEATURES • • • • • • 256MB (32M x 72) Unbuffered DDR SO-DIMM based on 32Mx8 DDR SDRAM JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) 2.
5V +/- 0.
2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz/166MHz All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock • ...

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HYMD232M726AJ8-H Unbuffered DDR SO-DIMM - Hynix Semiconductor

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