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EBE11UD8AGUA

Part Number	EBE11UD8AGUA
Manufacturer	Elpida Memory
Description	1GB DDR2 SDRAM SO-DIMM
Published	Mar 21, 2010
Detailed Description	DATA SHEET www.DataSheet4U.com 1GB DDR2 SDRAM SO-DIMM EBE11UD8AGUA (128M words × 64 bits, 2 Ranks) Specifications • De...
Datasheet	EBE11UD8AGUA PDF File

Overview

DATA SHEET www.
DataSheet4U.
com 1GB DDR2 SDRAM SO-DIMM EBE11UD8AGUA (128M words × 64 bits, 2 Ranks) Specifications • Density: 1GB • Organization ⎯ 128M words × 64 bits, 2 ranks • Mounting 16 pieces of 512M bits DDR2 SDRAM sealed in FBGA • Package: 200-pin socket type small outline dual in line memory module (SO-DIMM) ⎯ PCB height: 30.
0mm ⎯ Lead pitch: 0.
6mm ⎯ Lead-free (RoHS compliant) • Power supply: VDD = 1.
8V ± 0.
1V • Data rate: 667Mbps/533Mbps (max.
) • Four internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge operation for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period 7.
8μs at 0°C ≤ TC ≤ +85°C 3.
9μs at +85°C < TC ≤ +95°C • Operating case temperature range ⎯ TC = 0°C to +95°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation Document No.
E0918E20 (Ver.
2.
0) Date Published May 2007 (K) Japan Printed in Japan URL: http://www.
elpida.
com ©Elpida Memory, Inc.
2006-2007 EBE11UD8AGUA Ordering Information Data rate Mbps (max.
) Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) Contact pad Gold www.
DataS...

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