DatasheetsPDF.com

EBE21UE8ABFA

Elpida Memory
Part Number EBE21UE8ABFA
Manufacturer Elpida Memory
Description 2GB Unbuffered DDR2 SDRAM DIMM
Published Mar 21, 2010
Detailed Description PRELIMINARY DATA SHEET www.DataSheet4U.com 2GB Unbuffered DDR2 SDRAM DIMM EBE21UE8ABFA (256M words × 64 bits, 2 Ranks)...
Datasheet PDF File EBE21UE8ABFA PDF File

EBE21UE8ABFA
EBE21UE8ABFA

Overview
PRELIMINARY DATA SHEET www.
DataSheet4U.
com 2GB Unbuffered DDR2 SDRAM DIMM EBE21UE8ABFA (256M words × 64 bits, 2 Ranks) Specifications • Density: 2GB • Organization  256M words × 64 bits, 2 ranks • Mounting 16 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory module (DIMM)  PCB height: 30.
0mm  Lead pitch: 1.
0mm  Lead-free (RoHS compliant) • Power supply: VDD = 1.
8V ± 0.
1V • Data rate: 800Mbps/667Mbps/533Mbps/400Mbps (max.
) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms  Average refresh period 7.
8µs at 0°C ≤ TC ≤ +85°C 3.
9µs at +85°C < TC ≤ +95°C • Operating case temperature range  TC = 0°C to +95°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation Document No.
E0906E10 (Ver.
1.
0) Date Published June 2006 (K) Japan Printed in Japan URL: http://www.
elpida.
com Elpida Memory, Inc.
2006 EBE21UE8ABFA Ordering Information Data rate Mbps (max.
) 800 667 533 Component JEDEC speed bin (CL-tRCD-tRP) DDR2-800 (5-5-5) DDR2-667 (5-5-5) DDR2...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)